Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994

Chapter 2: Design Environments

Section 4 of 6

2.4 Component Level

The next level of abstraction that defines a class of design environments is the component level. Environments of this type are usually composed of primitives that perform a small number of arithmetic or logical operations. For example, an adder or a small block of memory are acceptable component-level primitives, but an entire processor or a fully interfaced bank of memory are generally not.

A number of different environments exist at the component level. Register transfer is an environment that is used to describe the design of processors. ISP is a language that is used to describe the instruction set of a computer and how those instructions are implemented. Even integrated-circuit packages, although quite variable in their functionality, form a component-level environment in common use. However, this is also a layout environment and so it will be discussed later.

2.4.1 Register-Transfer Environment

The first component-level environment of interest is register transfer [Bell, Grason and Newell]. In this environment, the components are specific hardware manipulations of control and data with connections showing the flow for the desired algorithm. This environment can be used to describe the instruction set of computers because it shows the flow of control in a processor that effects the machine's operation. It is also useful in the design of algorithms. Actual implementations of these components were used to teach hardware design to university students.

The components of the register-transfer environment are named after the components of the PMS environment. Their level of detail is much greater and fewer assumptions are made about the contents of a component. For example, register transfer has no processor but instead constructs one from control, memory, and data operations.

The set of register transfer components is shown in Fig. 2.15. There are four classes of components: control (K), memory (M), data/memory (DM), and transducers (T). The control and memory components are similar to their counterparts in the PMS environment. The data/memory component is similar to the PMS processor, although much less powerful. The transducer component combines the functions of the PMS transducer and the PMS data operation.

Two PMS components are missing from this list: the switch and the link. The switch is a type of control component in register transfer, as will be discussed. The link does not appear in the register-transfer environment because of the connection distinctions. Rather than describe a connection in terms of physical distance, register transfer distinguishes connections by their contents.

Fig 2.15
FIGURE 2.15 The components of the register-transfer environment. "K" is control; "D" is data; "M" is memory, and "T" is input/output.

Register transfer has four types of connections between components: bus, control, Boolean, and miscellaneous. The bus is a general-purpose data and control connection that passes synchronized information between components. Control connections are used to link the control components and also to invoke activity in other components. Boolean connections are special-purpose signals that aid the flow of execution by linking conditions with decision-making control components. Finally, miscellaneous connections exist to link these register-transfer components with external devices.

Every register-transfer design has exactly one Kbus component. This controls the bus connections for all other components and is the source of initial and terminal control that links the design with the outside world. In student hardware laboratories, where register-transfer modules were used most, this component provides the manual interface to the running circuit.

Flow of control is done with four components: Kb, Ksub, Ksm, and Kpm. The Kb component does a branch, conditional on a Boolean input. Only one of the two output connections will be invoked, causing that control module to execute next. The Ksub component executes a subroutine of control modules by invoking the first module, awaiting a completion signal on the return line, and then invoking the next sequential control component. The Ksm does a serial merge, invoking the next control component when any one input line is raised. This is useful in loops where multiple execution paths enter a single control stream. It is also useful for parallel execution control. Such a situation can exist if a single control-invocation line connects to multiple control components. Then the synchronization of these control paths can be accomplished with the Ksm or the Kpm components. The Kpm does a parallel merge that waits for all input lines to be invoked before it generates its own output.

All of these control components are used to construct a flow of execution in a register-transfer design. However, none of them cause any data to be manipulated. All data operations are controlled with the evoke component, Ke. The Ke acts like a subroutine call to a data component: It initiates the data operation, awaits completion, and then invokes the next sequential control component. All data components communicate between each other on the bus and communicate back to the control components via Boolean connections.

There are two internal data components: the DMgpa and the M. The DMgpa, or "general-purpose-arithmetic" component, is able to perform the simplest of arithmetic and logical operations. It holds two registers that it can move, add, subtract, complement, logically AND, logically OR, and shift. It generates Boolean signals that indicate numeric test results. This component is the workhorse of any algorithm done in the register-transfer environment. The M is the other internal component and it stores memory. To use it, both a memory address and a data value must pass across the bus on separate control cycles. The Boolean output signal is used in slower memories to indicate the completion of the operation. This allows other work to proceed in parallel with the memory access. The size and speed of the memory varies, yielding a subclass of these components.

Transducer components are used to convert between bus data and analog signals for external use. Input transducers can handle analog input, switch bank sensing, and keyboards. Output transducers can print, plot, and produce general analog signals.

Figure 2.16 shows an example of register-transfer layout that normalizes a floating point number. The two DMgpa components store and manipulate three values: a sign flag called Flag, the mantissa (Man) and the exponent (Exp). The top six components set the sign flag and ensure a positive mantissa. Following that, the mantissa is shifted until there is a "1" in its high bit (a normalized fraction is between one-half and one). Each shift of the mantissa requires an increment of the exponent to keep the overall value correct. When the number has been normalized, the sign flag is used to restore negative values.
Fig 2.16
FIGURE 2.16 Register-transfer layout to normalize a floating-point number. Shown complete with bus connections (thick) and data-evocation lines (dotted).

The bus-control component links the data buses and controls the execution of the algorithm. Many register-transfer designs are done without explicitly showing the data and Kbus components or any bus connections. Figure 2.17 shows the same algorithm without these datapath complexities. This makes the design simpler without sacrificing the detail of this environment, because the data components and their connectivity can be inferred from the control components.
Fig 2.17
FIGURE 2.17 Register-transfer layout to normalize a floating-point number. Shown without bus or data-evocation connections.

In addition to being a useful environment for algorithm specification, register-transfer designs are able to be built in hardware. Every component in the environment has associated electronic modules that can be wired together. Thus a working register-transfer machine can be built directly from these designs. Although these register-transfer modules are no longer used, the concepts in this environment are still valid and can be realized with other implementation methods.

Many hardware-description languages textually capture the same information as the register-transfer environment does. One language separates data structure from control [Baray and Su], similar to the distinction made in register transfer.

2.4.2 ISP Environment

Bell and Newell also defined a component-level environment for describing computers [Bell and Newell]. ISP, or instruction-set processor, is a language for describing the instructions in a processor and how they are implemented. Notation is provided to specify the machine organization, to manipulate machine registers, and to specify parallel or pipelined execution. For example, the statement:

(OP = 1) (M[OPERAND] AC; AC 0);

states that if OP is equal to 1 then two actions will occur in parallel: The value of the accumulator register AC will be deposited at memory location OPERAND and the accumulator will be cleared. This statement handles the decoding and execution of a "deposit and clear accumulator" instruction. Prior to such a statement, the meanings of every term must be defined. For example, the OP field may be defined as:

OP := M[PC]<0:2>

which means that the three high bits of memory-location PC define this field. Similarly, the meaning of PC, AC, and even the memory M must be explicitly defined. Thus ISP resembles a programming language, complete with declarations and executable statements.

Nonparallel sequencing is specified with the "next" clause, as in the following example:

(AC AC + T; next M[D] AC)

This ensures that the addition of T to AC is completed before the result is stored at memory location D. Determination of when an operation can be done in parallel is dependent on the architecture of the processor. This architecture is specified implicitly by the various ISP components and the operations that can be performed on them.

ISP is often used to describe computer instruction sets. It is a highly algorithmic environment, which leads one to believe that it should not be a component-level environment. However, there are direct associations between ISP statements and the machine registers that implement them because the text can be used to infer a diagram of the target machine. Thus ISP is another example of a component-level environment. These environments illustrate detailed electronic design without completely precise specification.

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