Electric contains a number of different design environments. As described earlier, these environments exist as technology objects in the database. The objects contain both procedural and tabular information that describes their contents. For example, the primitive components are represented by a linked list of node-prototype objects. However, the graphical description of these primitives is done procedurally with one routine that returns a count of polygons, and another routine that is repeatedly called to describe each polygon. This allows primitives to be arbitrarily parameterized for maximum flexibility.
Adding environments simply requires that the necessary tables and routines be coded into a module, and a technology object be created with pointers to this module. The routines are for initialization, special control, node description, arc description, and port description. The node-description routines actually take two forms, depending on whether the description is for display or for circuit analysis. Tabular information includes design rules, simulation characteristics, default sizes, connectivity information, behavior, reformatting data, layer patterns, and colors. Much of the information handled by routines is also coded tabularly.
Most of the environments in Electric are for layout of integrated circuits, there being many different processes and many variations within a process. For example, there are four different CMOS environments: an idealized version with one layer of metal [Griswold], a double-metal version for MOSIS design rules [Mukherjee], a double-polysilicon version for Canadian foundry design rules, and a special MOSIS version with round geometry. In addition to those for CMOS, there are environments for nMOS and Bipolar layout.
In non-IC design, there are environments for schematic capture and printed-circuit-board layout, and some high-level architectural environments such as one for digital filters [Kroeker]. It is even possible to do nonelectronic design with two environments: artwork for arbitrary graphics, and GEM for concurrent event specification [Lansky and Owicki]. The most interesting environment, however, is called "generic" because it contains many useful primitives for flexibility of design.
The generic environment allows the intermixing of all other environments by providing universal components and wires that have unrestricted connectivity. With the universal wire, a gate from the schematics environment can be connected to a transistor of the nMOS environment. The use of this wire is necessary because, although the two components can reside in the same cell, neither the basic wire of schematics nor the polysilicon or diffusion wires of nMOS can legally make the connection. The same reasoning applies to the use of the universal pin in connecting wires from different environments. The mixing of environments is useful for a number of purposes including process experimentation (mixing multiple IC-layout environments), IC-design shorthand (mixing layout and schematics), and system-level simulation (mixing IC and PC layout).
Another feature of the generic environment is the invisible wire, which can connect any components but does not make an electrical connection. This is useful for placing constraints on two objects regardless of their network relationship. An invisible wire can be constrained just like any other wire, but it carries no signals and does not appear in the fabrication output.
Also in the generic environment are special primitives that are useful in design. The Cell-Center component, for example, is a fiducial mark that, when placed in a cell, defines the origin for cursor-based manipulation of cell instances. The unrouted wire makes a connection and also indicates to routers that it should be replaced with correctly routed wires.
The MOS environments contain the high-level layout primitives that have been described in Chapter 2 (see Figs. 2.18 and 2.21). A transistor component is used to represent the intersection of polysilicon and diffusion so that the network can be easily maintained. There are two transistor primitives in each MOS environment: enhancement and depletion in nMOS; n-type and p-type in CMOS. There are also a host of contacts for connecting wires on the different layers, and a set of pins for connecting wires on the same layer.
An important escape hatch for IC design is the availability of pure layer components that allow arbitrary geometry to be produced when the higher-level primitives are not flexible enough. Of course, in an attempt to avoid such use, much attention has gone into planning the primitives to make them usable and powerful. For example, the contact-cut primitives automatically add extra cut polygons as their size grows large so that multiple components do not have to be used. Also, the transistor primitives allow an arbitrary path to be specified for serpentine description. It is therefore only the most unusual layout, typically analog, that needs the pure-layer components.
Another high-level aspect of MOS environments is the automatic placement of implants. In nMOS, this simply means that the depletion transistor includes the depletion-implant layer as part of its description. In CMOS however, all diffusion activity takes place in substrate or well implants, so all the transistors, diffusion wires, diffusion contacts, and diffusion pins must include implant information. Thus there are two sets of these components, one for each implant, and the correct version must always be used. Given this feature, the designer is able to work without consideration for implant placement because there is always enough of it automatically placed to encapsulate the circuitry properly.
The bipolar environments are significantly different from MOS environments, even though they are all for IC layout. Rather than having a few geometries for the simple field-effect transistor, it is necessary to provide total flexibility in the layout of junction transistors by allowing arbitrarily shaped bases, emitters, and collectors. Thus there are three primitives that combine to form a transistor. These primitives are complex since they describe the many bipolar layers necessary for base, emitter, and collector construction. There are also contacts and vias that make connections between conducting layers.
The schematic-capture environment contains the necessary components for digital and analog diagrams of circuits. On the digital side there are the logic gates AND, OR, XOR, Flip-Flop, and Buffer, all of which can be customized to handle any number of inputs and negate any signal. Negation is accomplished by placing an inverting bubble on the connecting wire rather than on the component. To the designer, this provides sufficient flexibility for the specification of negation and significantly reduces the number of primitives. In the database, there is simply a negating bit set on the wire, which makes the code for extracting logic somewhat more complex although not unmanageable. The Flip-Flop can be parameterized in its triggering (master-slave, positive, or negative) and in its function (RS type, JK type, D type, and so on). The Buffer primitive, when negated, becomes an inverter and can also have an enable line on it.
Analog components are provided in the schematics environment and can connect freely with the digital primitives. Included in this set is the Transistor (n-type, d-type, p-type, pnp, npn, JFET, MESFET, or dual-emitter), Resistor, Capacitor, Inductor, and Diode. All components can be parameterized with ratios and other relevant values.
There are some miscellaneous primitives useful in all schematic design. The Black-Box can contain any function and connect arbitrarily. The Power, Ground, Source, and Meter primitives are similarly general and can be used in simulation to indicate input and output graphically. Finally, an Off-Page connector is provided for network continuity between cells of the circuit. For truly unusual symbols, users can sketch their own bodies using the artwork environment described next.
The schematic-capture environment also provides buses and bus taps for aggregating signals. Although the logic gates can accept buses, it is up to the various analysis and synthesis tools to handle this correctly and ensure that the signal counts are sensible. Individual network naming is available from the network-maintainer tool described later.
As an exercise in expanding the power of Electric, some nonelectrical environments were created. The most interesting is the artwork environment, which contains graphic primitives for arbitrary image creation. Not only is this useful for the generation of sketches, but also it can augment VLSI design by adding artwork to layout or by defining new graphic symbols. This environment is so powerful that it was used to generate all the figures in this book. The availability of a general-purpose drawing facility also allows the simulators to represent waveform plots in the database.
The bulk of the graphics in the artwork environment is done with primitive components that appear as polygons, text, circles, arrowheads, and so on. There are also wires that can draw lines and curves but, in general, the notion of connectivity is less important to a sketching system.
When the artwork environment is used, many of the user interface settings must be changed because the command set for VLSI design is not the same as that is needed for sketching. This argument is also true for the distinction between layout and schematics: No two design environments can conveniently share exactly the same set of commands for their use. Thus, for each environment that is not standard VLSI layout, there is a command file that retailors the user interface for the best use. This file changes defaults, rearranges menus, and creates new commands appropriate to the different style of design.
|Previous||Table of Contents||Next||Static Free Software|