Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994
Chapter 5: Static Analysis Tools
This chapter has illustrated a number of techniques for
the data-free examination of VLSI circuits.
Such static analyses require a full topological description of the circuit
that is often a product of node extraction.
Geometric design rules check the layout of a circuit, and electrical rules check
Verification tools check individual specifications to ensure
that the design will perform as intended.
The next chapter deals with actual performance considerations that can
be analyzed by treating a circuit dynamically.
What is the problem with raster-based design-rule checking that does not
occur with raster-based node extraction?
How can network-comparison methods fully describe the differences between
How would you program a preprocessor to convert design rules into state-based
design-rule checking tables?
Why is timing verification more user-intensive than is design-rule checking?
Why is the functional verification of asynchronous circuits so difficult?
Why are rule-based systems an ideal choice for implementation of
What is the drawback of hierarchical design rule checking?
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