Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994
Chapter 6: Dynamic Analysis Tools
This chapter was contributed by Robert W. Hon,
Cadence Design Systems Inc.
The state of the art demands that designers make compromises in size
of design versus level of detail in simulation.
performing simulators can simulate large designs, but not in
sufficient detail to catch subtle errors of the type likely to occur
in a process that still involves a great deal of low-level design.
Circuit-level simulators can provide all the detail that a designer is
likely to need, but cannot process large designs.
A particularly effective approach is to use detailed (circuit-level)
simulation to check critical functional or timing paths, and less-detailed
simulation for the remainder of the design.
The critical sections
can be determined using human insight, or through the use of higher-level
simulations that identify potential problems in the design.
Although thorough static-analysis techniques proliferate, they still do
not replace the actual use of data in debugging a design.
therefore of continued importance in a CAD system.
will have to keep up with the rapidly changing needs of design
environments, both in their capabilities and in their style of use.
Invent a more abstract logic block that could replace the cross-coupled
NOR gates of the example in the section, Event-Driven Simulation.
Give its extended truth table.
Show the event queue that results from simulating your logic block under the same
assumptions as before (unit gate delay, zero wire delay).
Build a truth table for an AND gate that includes the four states:
0, 1, X, and Z (resistive-pullup high).
What problems occur when simulating bidirectional MOS transistors?
How can these be overcome?
How can more accurate models of time improve the quality of simulation that
is concerned only with logic values at nodes (and not time)?
How can hierarchy aid in simulation?
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