Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994
Chapter 11: Electric
11.6 Designing a Chip
To illustrate the use of Electric, this section will describe the
construction of a static-memory chip [Lyon and Schediwy].
This chip makes use of a novel four-transistor bit of static memory.
The fundamental memory cell is logically designed using the schematics
environment (see Fig. 11.12).
An equivalent CMOS layout is then produced without concern for compact
spacing (see Fig. 11.13).
For proper layout efficiency, alternate bits of memory are different,
so two bits define the leaf cell of the design.
These bits can be compacted by the one-dimensional compacter (see Fig. 11.14)
and then compacted further by rearranging components and recompacting
(see Fig. 11.15).
Schematic for four-transistor static-memory cell.
CMOS layout for four-transistor static-memory cell.
CMOS layout for two four-transistor static-memory cells.
Compacted CMOS layout for two four-transistor static-memory cells.
To create a 128 × 32-bit array of memory, six levels of hierarchy
are employed to build a 4 × 2 array, a 4 × 4
array, a 16 × 8 array, a 64 × 8 array, a
64 × 32 array,
and a 128 × 32 array (see Fig. 11.16).
Note that each level of hierarchy actually connects its subcells with
little stitches so that the overall connectivity is maintained.
These stitches are automatically created by the router.
Also, each level of hierarchy must export all unstitched ports to the
This is done automatically by the array-based layout commands.
Hierarchical organization for 128 × 32 array of static-memory cells.
Once the basic memory array is created, driving circuitry must be placed
on the edges.
A word (32-bit) driver for a single word is designed to pitch match the memory
(see Fig. 11.17) and the driver is arrayed using hierarchy.
The block of 128 drivers attaches to the bottom of the memory array.
Similar drivers and decoders are built on the sides.
The overall floor-plan, including pads, is shown in Fig. 11.18.
This layout contains 32,650 transistors, described with 110 cells.
Word line driver for static-memory array.
As an indication of the complexity of Electric, this circuit consumes
1.4 megabytes of disk space.
Although this is not small, it does contain more information than typical design
It can be read in 50 seconds and written in 30 seconds (on a SUN/3 workstation).
Netlist generation takes only 15 seconds (these figures were compiled in 1986, when computers
were significantly slower).
Floor-plan of static-memory chip.