Function: Crc
Summary:
The Crc function implements both the CRC (cyclic redundancy check) encoder
and decoder. The input stream represents a polynomial which is divided
by the generator polynomial. The remainder of the division is the
parity or checksum information. When encoding, parity information
is generated. When decoding, the parity information should be zero if
no errors have occured.
The single bit input X is clocked in with R HIGH. When the entire
data block has been clocked in, R is brought LOW Degree cycles
and the parity bits are clocked out on Z.
When decoding, the ERR signal can be examined after the last bit of the
data block has been clocked in to determine if any errors have occurred.
The generator polynomial is either constant or variable. Variable
polynomials are input on the GEN bus. GEN[i] is the value of the x^i term
in the polynomial. X^Degree is always 1. When a constant polymnomial is
desired, ConstPoly is set to the value
cDegree-1*2^Degree-1 + ... + c2+2^2 + c1*2^1 + c0*2^0.
Function:
Z=X mod GEN
ERR=(X mod GEN)==0
Signals:
Z: 1-bit output stream
X: 1-bit input stream
R: 1-bit reset control signal
ERR: 1-bit error detection output (only if OutputErr is selected)
GEN: Degree-bit generator polynomial.
Parameters:
Name: actual module name
Degree: Degree of the generator polynomial
ConstPoly: Value of the generator poynomial or zero for variable polynomial
OutputErr: select to output ERR, deselect for no ERR
Verilog Usage:
Name(X,R,GEN,Z,ERR); (ConstPoly=0,OutputErr selected)
Name(X,R,Z,ERR); (ConstPoly>0,OutputErr selected)
Name(X,R,GEN,Z); (ConstPoly=0,OutputErr deselected)
Name(X,R,Z); (ConstPoly>0,OutputErr deselected)
Version: $Id: Crc.help,v 1.2 1994/08/19 16:37:48 peter Exp $