LeadingZero
Summary:
The LeadingZero function counts leading zeros or ones from the input, X,
to form the output, Z. Counting starts from the MSB of X.
The LSB's of Z indicates the number of leading 0's or 1's, while the MSB
indicates that X is all zeros or ones. Note that when the MSB of Z is set,
the LSB's of Z are set to all ones for Leading0 detection but are set to
all zeros for Leading1 detection.
LeadingZero uses a very fast architecture (compared to Norm). It behaves
very similar to Norm, but it does not normalize the input as Norm does.
If the width of X is not a power of two, X is left shifted to make its width
a power of two. Because the padding for left shift is 0, the behaviors of
leading 0 and 1 detection are not symmetrical.
Following are a few examples showing the operation of LeadingZero function.
The width of output Z is ceil(log2(width(X)))+1.
Leading0
Input X Left shift Output Z
-------------------------------------------------------
001100 00110000 0010
000000 00000000 1111
00000000 00000000 1111
Leading1
Input X Left shift Output Z
-------------------------------------------------------
110011 11001100 0010
111111 11111100 0110
11111111 11111111 1000
Note that, for the X=111111 case, the MSB of Z is not set because it is not
all ones after left shift.
Function:
Z[log2(width(X))-1:0] : number of leading 0's or 1's
Z[log2(width(X))] : all zeros or ones, depending on Leading0
Signals:
Z: output width chosen automatically=ceil(log2(width(X)))+1
X: Width wide input
Parameters:
Name: actual module name
Width: width of the X input
Leading0: count leading zeros when selected, count leading ones otherwise
Verilog Usage:
Name(X,Z);
Version: $Id: LeadingZero.help,v 1.6 1996/11/26 03:04:23 aaron Exp $