Given that it may take weeks or months to get an integrated circuit manufactured, it should not be surprising that designers often spend large amounts of time analyzing their layouts to avoid costly mistakes. It can be difficult, if not impossible, to cure design flaws, particularly on integrated circuits, so the old saw "an ounce of prevention..." is very true. This chapter describes some of the computer aids to circuit analysis that help to guarantee correctly manufactured parts.
A VLSI circuit is a complex maze of paths that combine to effect an overall function. There are a number of ways to analyze these paths to ensure that they are correct. One method is to place test data on certain probe points and to follow those data conceptually as they flow through the circuit. Output points can then be observed to determine whether the circuit has properly handled the data. The selection of input data is called test-vector generation and the observation of those data as they flow through the computer representation of a circuit is called simulation. The overall process is called dynamic analysis, because it examines an energized, time-functioning circuit. Both of these processes presume that the design is so complex that the only way to verify it is to try a sample of its capabilities rather than to analyze every part. Thus the proper selection of test vectors is crucial and the accuracy of the simulation can tell much about the circuit. These dynamic analysis tools will be discussed in Chapter 6.
Of interest in this chapter is the other kind of analysis, called static analysis because it examines a circuit that is devoid of input data and therefore does not change over time. There are two basic types of static analysis: rule checking and verification. Rule checking ensures that a circuit obeys the restrictions placed on it by the design environment and is further divided into geometric design rules, which are concerned with the physical placement of the layout, and electrical rules, which examine the interconnection of the layout. Verification ensures that a circuit obeys the restrictions placed on it by the designer so that the intended behavior agrees with the actual behavior. In functional verification, the operation of parts is aggregated into an overall function for the circuit. In timing verification, the delay of parts is aggregated into an overall speed for the circuit.
Computer analysis of VLSI circuits can be very time consuming because of the size of the designs and the required thoroughness of analysis. One way to reduce this time is to perform analysis as the circuit is being designed. Many small tasks can be done in the idle time between commands to a CAD system. In addition, simple bookkeeping done incrementally can save much time later. If error feedback can be supplied immediately, vast amounts of redesign time can be saved. The more responsive a CAD system is in its analysis, the better it will be for complex VLSI design.
|Previous||Table of Contents||Next||Static Free Software|